TE28F640P30T85 データシートの表示（PDF） - Numonyx -> Micron

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TE28F640P30T85

Numonyx™ StrataFlash® Embedded Memory (P30)

Numonyx -> Micron 

P30

1.0

1.1

Introduction

This document provides information about the Numonyx™ StrataFlash® Embedded

Memory (P30) product and describes its features, operation, and specifications.

The Numonyx™ StrataFlash® Embedded Memory (P30) product is the latest generation

of Numonyx™ StrataFlash® memory devices. Offered in 64-Mbit up through 512-Mbit

densities, the P30 device brings reliable, two-bit-per-cell storage technology to the

embedded flash market segment. Benefits include more density in less space, high-

speed interface, lowest cost-per-bit NOR device, and support for code and data

storage. Features include high-performance synchronous-burst read mode, fast

asynchronous access times, low power, flexible security options, and three industry

standard package choices. The P30 product family is manufactured using Intel* 130 nm

ETOX™ VIII process technology.

The P30 product family is also planned on the Intel* 65nm process lithography. 65nm

AC timing changes are noted in this datasheet, and should be taken into account for all

new designs.

Nomenclature

1.8 V:

3.0 V:

9.0 V:

VCC (core) voltage range of 1.7 V – 2.0 V

VCCQ (I/O) voltage range of 1.7 V – 3.6 V

VPP voltage range of 8.5 V – 9.5 V

Block:

Main block:

Parameter block:

Top parameter device:

Bottom parameter device:

A group of bits, bytes, or words within the flash memory array that erase simultaneously

when the Erase command is issued to the device. The P30 has two block sizes: 32-KByte

and 128-KByte.

An array block that is usually used to store code and/or data. Main blocks are larger than

parameter blocks.

An array block that is usually used to store frequently changing data or small system

parameters that traditionally would be stored in EEPROM.

A device with its parameter blocks located at the highest physical address of its memory

map.

A device with its parameter blocks located at the lowest physical address of its memory

map.

1.2

Acronyms

BEFP:

CUI:

MLC:

OTP:

PLR:

PR:

RCR:

Buffer Enhanced Factory Programming

Command User Interface

Multi-Level Cell

One-Time Programmable

Protection Lock Register

Protection Register

Read Configuration Register

Datasheet

6

November 2007

Order Number: 306666-11

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