LH28F160BGHR-TTL10 データシートの表示（PDF） - Sharp Electronics
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LH28F160BGHR-TTL10 Datasheet PDF : 36 Pages
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LH28F160BG-TL/BGH-TL
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 10 and
Fig. 11 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the VPP ≤ VPPLK, read operations from the
status register, identifier codes, or blocks are
enabled.
Device operations are selected by writing specific
commands into the CUI. Table 2 defines these
commands.
Table 1 Bus Operations
MODE
NOTE RP# CE# OE# WE# ADDRESS VPP DQ0-15 RY/BY#
Read
1, 2, 3, 8 VIH or VHH VIL
VIL
VIH
X
X
DOUT
X
Y Output Disable
3 VIH or VHH VIL
VIH
VIH
X
X High Z X
Standby
3 VIH or VHH VIH
X
X
X
X High Z X
R Deep Power-Down
4
VIL
X
X
X
X
X High Z High Z
Read Identifier Codes
8 VIH or VHH VIL
VIL
VIH See Fig. 2 X (NOTE 5) High Z
Write
3, 6, 7, 8 VIH or VHH VIL
VIH
VIL
X
X
DIN
X
A NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
N not altered.
I 2. X can be VIL or VIH for control pins and addresses, and
4. RP# at GND±0.2 V ensures the lowest deep power-
down current.
5. See Section 4.2 for read identifier code data.
6. VIH < RP# < VHH produce spurious results and should
3.
VPPLK or VPPH1/2 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2 voltages.
RY/BY# is VOL when the WSM is executing internal
M block erase or word write algorithm. It is high-impedance
when the WSM is not busy, in block erase suspend
I mode (with word write inactive), word write suspend
P R E L mode or deep power-down mode.
not be attempted.
7. Refer to Table 2 for valid DIN during a write operation.
8. Don’t use the timing both OE# and WE# are VIL.
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