LH28F160BV-TL データシートの表示（PDF） - Sharp Electronics

部品番号

コンポーネント説明

メーカー

LH28F160BV-TL

16 M-bit (1 MB x 16) Smart 3 Flash Memories

Sharp Electronics 

LH28F160BG-TL/BGH-TL

BLOCK ORGANIZATION

This product features an asymmetrically-blocked Parameter Blocks : The boot block architecture

architecture providing system memory integration. includes parameter blocks to facilitate storage of

Each erase block can be erased independently of frequently update small parameters that would

the others up to 100 000 times. For the address normally require an EEPROM. By using software

locations of the blocks, see the memory map in techniques, the byte-rewrite functionality of

Fig. 1.

EEPROMs can be emulated. Each boot block

component contains six parameter blocks of 4 k

Boot Blocks : The two boot blocks are intended to

replace a dedicated boot PROM in a micro-

processor or microcontroller-based system. The

boot blocks of 4 k words (4 096 words) feature

hardware controllable write-protection to protect the

crucial microprocessor boot code from accidental

modification. The protection of the boot blocks is

controlled using a combination of the VPP, RP# and

WP# pins.

BLOCK DIAGRAM

DQ0-DQ15

words (4 096 words) each. The parameter blocks

are not write-protectable.

Main Blocks : The reminder is divided into main

Y blocks for data or code storage. Each 16 M-bit

device contains thirty-one 32 k words (32 768

I N A R words) blocks.

A0-A19

OUTPUT

BUFFER

INPUT

BUFFER

E L I M INPUT

BUFFER

Y

DECODER

RADDRESS

PLATCH

X

DECODER

IDENTIFIER

REGISTER

STATUS

REGISTER

DATA

COMPARATOR

Y GATING

31

32 k-WORD

MAIN BLOCKS

COMMAND

USER

INTERFACE

I/O

LOGIC

VCC

CE#

WE#

OE#

RP#

WP#

WRITE

STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

RY/BY#

VPP

VCC

GND

ADDRESS

COUNTER

-3-

Share Link: