LH28F160BGHR-TTL10 データシートの表示（PDF） - Sharp Electronics
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LH28F160BGHR-TTL10 Datasheet PDF : 36 Pages
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LH28F160BG-TL/BGH-TL
of status (versus software polling) and status The Automatic Power Saving (APS) feature
masking (interrupt masking for background block substantially reduces active current when the
erase, for example). Status polling using RY/BY# device is in static mode (addresses not switching).
minimizes both CPU overhead and system power In APS mode, the typical ICCR current is 3 mA at
consumption. When low, RY/BY# indicates that the 2.7 V VCC.
WSM is performing a block erase or word write.
RY/BY#-High-impedance indicates that the WSM is When CE# and RP# pins are at VCC, the ICC
ready for a new command, block erase is CMOS standby mode is enabled. When the RP#
suspended (and word write is inactive), word write
is suspended, or the device is in deep power-down
mode.
The access time is 100 ns or 120 ns (tAVQV) at the
VCC supply voltage range of 2.7 to 3.6 V over the
temperature range, 0 to +70°C (LH28F160BG-TL)/
–25 to +85°C (LH28F160BGH-TL).
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
Y valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
I N A R and the status register is cleared.
PRELIM
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