LH28F160BV-TL データシートの表示（PDF） - Sharp Electronics
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LH28F160BV-TL Datasheet PDF : 36 Pages
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LH28F160BG-TL/BGH-TL
2 PRINCIPLES OF OPERATION
The LH28F160BG-TL/BGH-TL Smart 3 flash software to suspend a word write to read data from
memories include an on-chip WSM to manage any other flash memory array location.
block erase and word write functions. It allows for :
fixed power supplies during block erasure and word
2.1 Data Protection
write, and minimal processor overhead with RAM- Depending on the application, the system designer
like interface timings.
may choose to make the VPP power supply
switchable (available only when memory block
After initial device power-up or return from deep
power-down mode (see Table 1 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure and word writing. All functions
associated with altering memory contents—block
erase, word write, status and identifier codes—are
accessed via the CUI and verified through the
status register.
erases or word writes are required) or hardwired to
VPPH1/2. The device accommodates either design
practice and encourages optimization of the
processor-memory interface.
Y When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase or word
R write command sequences, provides protection
from unwanted operations even when high voltage
A is applied to VPP. All write functions are disabled
when VCC is below the write lockout voltage VLKO
or when RP# is at VIL. The device’s blocks locking
N capability provides additional protection from
Iinadvertent code or data alteration by gating erase
Commands are written using standard micro-
processor write timings. The CUI contents serve as
M input to the WSM, which controls the block erase
I and word write. The internal algorithms are
regulated by the WSM, including pulse repetition,
L internal verification and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
E outputs array data, accesses the identifier codes or
outputs status register data.
R Interface software that initiates and polls progress
of block erase and word write can be stored in any
P block. This code is copied to and executed from
and word write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial
system RAM during flash memory updates. After device power-up or after exit from deep power-
successful completion, reads are again possible via down mode, the device automatically resets to read
the Read Array command. Block erase suspend array mode. Five control pins dictate the data flow
allows system software to suspend a block erase to in and out of the component : CE#, OE#, WE#,
read/write data from/to blocks other than that which RP# and WP#. CE# and OE# must be driven
is suspended. Word write suspend allows system active to obtain data at the outputs. CE# is the
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