LH28F160BGHR-TTL10 データシートの表示（PDF） - Sharp Electronics
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LH28F160BGHR-TTL10 Datasheet PDF : 36 Pages
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LH28F160BG-TL/BGH-TL
device selection control, and when active enables As with any automated device, it is important to
the selected memory device. OE# is the data assert RP# during system reset. When the system
output (DQ0-DQ15) control and when active drives comes out of reset, it expects to read from the flash
the selected memory data onto the I/O bus. WE# memory. Automated flash memories provide status
must be at VIH and RP# must be at VIH or VHH. information when accessed during block erase or
Fig. 9 illustrates read cycle.
word write modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
3.2 Output Disable
not occur because the flash memory may be
With OE# at a logic-high level (VIH), the device providing status information instead of array data.
outputs are disabled. Output pins (DQ0-DQ15) are
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ15 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase or word write, the
device continues functioning, and consuming active
power until the operation completes.
3.4 Deep Power-Down
SHARP’s flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
Y controlled by the same RESET# signal that resets
the system CPU.
R 3.5 Read Identifier Codes
The read identifier codes operation outputs the
A manufacture code and device code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
I N with its proper algorithms.
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
M places output drivers in a high-impedance state and
I turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time tPHQV is required
after return from power-down until initial memory
L access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
E reset to read array mode and status register is set
to 80H.
R During block erase or word write modes, RP#-low
will abort the operation. RY/BY# remains low until
P the reset operation is complete. Memory contents
FFFFF
00002
00001
00000
Reserved for
Future Implementation
Device Code
Manufacture Code
Fig. 2 Device Identifier Code Memory Map
3.6 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.
being altered are no longer valid; the data may be
partially erased or written. Time tPHWL is required
The Block Erase command requires appropriate
after RP# goes to logic-high (VIH) before another command data and an address within the block to
command can be written.
be erased. The Word Write command requires the
command and address of the location to be written.
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