PI74FCT162652T データシートの表示（PDF） - Pericom Semiconductor
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PI74FCT162652T Datasheet PDF : 6 Pages
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PI74FCT16652/162652T
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PI74FCT162652T
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Product Features:
Common Features:
• PI74FCT16652T and PI74FCT162652T are high-speed, low
power devices with high current drive.
• Vcc=5V±10%
• Hysteresis on all inputs
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
PI74FCT16652T Features:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce)
< 1.0V at VCC = 5V, TA = 25°C
PI74FCT162652T Features:
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce)
< 0.6V at VCC = 5V, TA = 25°C
Fast CMOS 16-Bit
Registered Transceivers
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16652T and PI74FCT162652T are 16-bit registered
transceivers organized as two independent 8-bit bus transceivers
designed with 3-state D-type flip-flops and control circuitry
arranged for multiplexed transmission of data directly from the
data bus or from the internal storage registers. Each 8-bit transceiver
utilizes the enable controls (xOEAB and x OEBA) to control the
transceiver functions. The Select (xSAB and xSBA) control pins
are used to select either real-time or stored data transfer. The
circuitry used for select control will eliminate the typical decoding
glitch that occurs in a multiplexer during the transition between
real-time and stored data. A low input level selects real-time data
and a high selects stored data.
The PI74FCT16652T output buffers are designed with a Power-
Off disable allowing “live insertion” of boards when used as
backplane drivers.
The PI74FCT162652T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
Logic Block Diagram
1OEAB
1OEBA
1CLKBA
1SBA
1CLKAB
1SAB
1A0
A REG
D
C
B REG
D
C
2OEAB
2OEBA
2CLKBA
2SBA
2CLKAB
2SAB
2A0
1B0
A REG
D
C
B REG
D
C
2B0
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
1
PS2079A 01/15/95
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