CY7C197D データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C197D Datasheet PDF : 8 Pages
| |||
PRELIMINARY
CY7C197D
Thermal Resistance[4]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)[4]
Thermal Resistance
(Junction to Case)[4]
AC Test Loads and Waveforms[5]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
All-Packages
TBD
TBD
Unit
°C/W
°C/W
10-ns Device
OUTPUT
Z = 50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50 Ω
1.5V
(a)
30 pF*
3.0V
GND
10%
< tr
ALL INPUT PULSES
90%
90%
10%
< tr
12, 15 -ns Devices
5V
OUTPUT
R1 480 Ω
High-Z characteristics: R1 480Ω
5V
OUTPUT
Equivalent to: THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
30 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
(b)
5 pF
INCLUDING
JIG AND
SCOPE (c)
R2
255Ω
Switching Characteristics Over the Operating Range[6]
7C197D-10
7C197D-12
7C197D-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tpower[7]
VCC(typical) to the first access
100
100
100
µs
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Output Hold from Address Change
3
3
3
ns
tACE
tLZCE
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[8]
CE HIGH to High Z[8, 9]
10
12
15
ns
3
3
3
ns
5
5
7
ns
tPU
CE LOW to Power-Up
0
0
0
ns
tPD
CE HIGH to Power-Down
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
Write Cycle[10]
0
ns
tWC
Write Cycle Time
10
12
15
ns
tAW
Address Set-Up to Write End
7
9
10
ns
Notes:
5. tr = < 3 ns for all speeds.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
9. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05458 Rev. *C
Page 3 of 8
Share Link: 