CY7C197N データシートの表示（PDF） - Cypress Semiconductor
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CY7C197N Datasheet PDF : 7 Pages
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CY7C197N
AC Test Loads and Waveforms[5]
5V
OUTPUT
R1 329Ω
5V
OUTPUT
R1 329Ω
30 pF
INCLUDING
JIG AND
SCOPE
R2
5 pF
R2
202Ω
255Ω
(255Ω MIL) INCLUDING
(255Ω MIL)
JIG AND
(a)
SCOPE (b)
3.0V
GND
10%
< tr
Equivalent to: THÉVENIN EQUIVALENT
125Ω
OUTPUT
1.90V
Commercial
ALL INPUT PULSES
90%
90%
10%
< tr
Switching Characteristics Over the Operating Range[8]
-25
-45
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
tLZCE
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[9]
CE HIGH to High Z[9, 10]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
WRITE CYCLE[11]
25
45
ns
25
45
ns
3
3
ns
25
45
ns
3
3
ns
0
11
0
15
ns
0
0
ns
20
30
ns
tWC
Write Cycle Time
25
45
ns
tSCE
CE LOW to Write End
20
40
ns
tAW
Address Set-Up to Write End
20
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
20
30
ns
tSD
Data Set-Up to Write End
15
20
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[9]
WE LOW to High Z[9, 10]
0
0
ns
3
3
ns
0
11
0
15
ns
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
7. tr = < 5 ns for the -25 and slower speeds.
8. Test conditions assume signal transition time of 5 ns or less for -25 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
10. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 001-06495 Rev. **
Page 3 of 7
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