74HC137DB,118 データシートの表示（PDF） - NXP Semiconductors.

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74HC137DB,118

3-to-8 line decoder, demultiplexer with address latches; inverting

NXP Semiconductors. 

Nexperia

74HC137

3-to-8 line decoder, demultiplexer with address latches; inverting

Table 7. Dynamic characteristics …continued

GND = 0 V; tr = tf = 6 ns; CL = 50 pF.

Symbol Parameter

Conditions

th

hold time

An to LE; see Figure 8

VCC = 2.0 V

VCC = 4.5 V

VCC = 6.0 V

[1] tpd is the same as tPHL, tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CL  VCC2  fo) = sum of outputs.

11. Waveforms

Min

Typ

Max Unit

-

-

45 ns

-

-

9 ns

-

-

8 ns

$Q(LQSXW 90

<QRXWSXW

W3+/

90

W3/+

W7+/

W7/+

DDE

Fig 6.

VM = 0.5  VI.

Waveforms showing the address input (An) and enable input (E2) to output (Yn) propagation delays and

the output transition times

74HC137

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 23 December 2015

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