HIP6301V データシートの表示（PDF） - Renesas Electronics
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HIP6301V Datasheet PDF : 20 Pages
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HIP6301V, HIP6302V
function of the Channel Frequency, as explained previously.
Also note the pulses on the COMP terminal. These pulses
are the current correction signal feeding into the comparator
input (see Figure 1).
Figure 5 shows the regulator operating from an ATX supply.
In this figure, note the slight rise in PGOOD as the 5V supply
rises.The PGOOD output stage is made up of NMOS and
PMOS transistors. On the rising VCC, the PMOS device
becomes active slightly before the NMOS transistor pulls
“down”, generating the slight rise in the PGOOD voltage.
DELAY TIME
PWM 1
OUTPUT
PGOOD
VCORE
5V
VCC
VIN = 12V
FIGURE 3. START-UP OF 4-PHASE SYSTEM OPERATING
AT 500kHz
DELAY TIME
V COMP
PGOOD
VCORE
5V
VCC
VIN = 12V
FIGURE 4. START-UP OF 4-PHASE SYSTEM OPERATING
AT 200kHz
12V ATX
SUPPLY
PGOOD
VCORE
5V ATX
SUPPLY
VIN = 5V, CORE LOAD CURRENT = 31A
FREQUENCY 200kHz
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
Note that Figure 5 shows the 12V gate driver voltage
available before the 5V supply to the controller has reached
its threshold level. If conditions were reversed and the 5V
supply was to rise first, the start-up sequence would be
different. In this case the controller may sense an
overcurrent condition due to charging the output capacitors.
The supply would then restart and go through the normal
soft-start cycle.
Dynamic VID
The HIP6301V and HIP6302V require up to two full clock
cycles to detect a change in the VID code. VID code
changes that are not valid for at least two cycles may or may
not be detected. Once detected, the controller waits an
additional two-cycle wait period to be certain the change is
stable. After the two-cycle wait period, the DAC begins
stepping toward the new VID setting in 25mV increments.
The DAC makes one 25mV step every two clock cycles. For
example, a 500kHz system detecting a change from 1.300V
to 1.800V requires between 84ms and 88ms to complete the
change.
If a new VID code is detected during a DAC change and the
DAC can continue toward the new VID code without
changing direction, processing continues without
interruption. If a new VID code is detected during a DAC
change and the DAC has to change direction in order to
proceed toward then new VID code, processing halts. A
two-cycle wait period is initiated and processing continues
as above. These decisions are made with reference to the
transitional DAC value rather than the original target value.
FN9034 Rev 3.00
May 5, 2008
Page 10 of 20
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