HIP6301V データシートの表示（PDF） - Renesas Electronics

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HIP6301V

Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller

Renesas Electronics 

HIP6301V, HIP6302V

1.85V

1.85V

VREF

VCORE

5.00V

5.00V

PGOOD

VID CHANGE

50µs/DIV

FIGURE 6. VCORE TRACKING THE REFERENCE VOLTAGE

AFTER A 1.85V TO 1.10V CHANGE COMMAND

VCORE

1.10V

VREF

1.10V

5.00V

PGOOD

5.00V

VID CHANGE

50µs/DIV

FIGURE 7. VCORE TRACKING THE REFERENCE VOLTAGE

AFTER A 1.10V TO 1.85V CHANGE COMMAND

Fault Protection

The HIP6301V and HIP6302V protect the microprocessor

and the entire power system from damaging stress levels.

Within the controller, both overvoltage and overcurrent

circuits are incorporated to protect the load and regulator.

Overvoltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE overvoltage condition is detected when the

VSEN pin goes more than 15% above the programmed VID

level.

The overvoltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning VCC high to initiate a

POR and soft-start sequence.

During a latched overvoltage, the PWM outputs will be

driven either low or three state, depending upon the VSEN

FN9034 Rev 3.00

May 5, 2008

input. PWM outputs are driven low when the VSEN pin

detects that the CORE voltage is 15% above the

programmed VID level. This condition drives the PWM

outputs low, causing in the lower or MOSFETs to conduct

and shunt the CORE voltage to ground to protect the load.

If after this event, the CORE voltage falls below the

overvoltage limit (plus some hysteresis), the PWM outputs

will be three state. The HIP6601 family drivers pass the

three state information along, and shuts off both upper and

lower MOSFETs. This prevents “dumping” of the output

capacitors back through the lower MOSFETs, avoiding a

possibly destructive ringing of the capacitors and output

inductors. If the conditions that caused the overvoltage still

persist, the PWM outputs will be cycled between three state

and VCORE clamped to ground, as a hysteretic shunt

regulator.

Undervoltage

The VSEN pin also detects when the CORE voltage falls

more than 10% below the VID programmed level. This

causes PGOOD to go low, but has no other effect on

operation and is not latched. There is also hysteresis in this

detection point.

Overcurrent

In the event of an overcurrent condition, the overcurrent

protection circuit reduces the average current delivered to

less than 25% of the current limit. When an overcurrent

condition is detected, the controller forces all PWM outputs

into a three state mode. This condition results in the gate

driver removing drive to the output stages. The controller

goes into a wait delay timing cycle that is equal to the

soft-start ramp time. PGOOD also goes “low” during this time

due to VSEN going below its threshold voltage.To lower the

average output dissipation, the soft-start initial wait time is

increased from 32 to 2048 cycles, then the soft-start ramp is

initiated. At a PWM frequency of 200kHz, for instance, an

overcurrent detection would cause a dead time of 10.24ms,

then a ramp of 10.08ms.

At the end of the delay, PWM outputs are restarted and the

soft-start ramp is initiated. If a short is present at that time,

the cycle is repeated. This is the hiccup mode.

Figure 8 shows the supply shorted under operation and the

hiccup operating mode previously described. Note that due

to the high short circuit current, overcurrent is detected

before completion of the start-up sequence so the delay is

not quite as long as the normal soft-start cycle.

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