CS5124XDR8G データシートの表示（PDF） - ON Semiconductor

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CS5124XDR8G

High Performance, Integrated Current Mode PWM Controllers

ON Semiconductor 

CS5124

PIN #

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PACKAGE PIN DESCRIPTION

Pin

Description

VCC

BIAS

VCC Power Input Pin.

VCC Clamp Output Pin. This pin will control the gate of an N−channel MOSFET that in turn regulates Vcc. This pin is

internally clamped at 15 V when the IC is in sleep mode.

UVLO Sleep and under voltage lockout pin. A voltage greater than 1.8 V causes the chip to “wake up” however the GATE

remains low. A voltage greater than 2.6 V on this pin allows the output to switch.

SS Soft−Start Capacitor Pin. A capacitor placed between SS and GROUND is charged with 10 mA and discharged with

10 mA. The Soft−Start capacitor controls both Soft−Start time and hiccup mode frequency.

VFB

ISENSE

GATE

Voltage Feedback Pin. The collector of an optocoupler is typically tied to this pin. This pin is pulled up internally by a

4.3 kW resistor to 5.0 V and is clamped internally at 2.9 V (2.65 V). If VFB is pulled > 4.0 V, the oscillator is disabled

and GATE will stay high. If the VFB pin is pulled < 0.49 V, GATE will stay low.

Current Sense Pin. This pin is connected to the current sense resistor on the primary side. If VFB is floating, the

GATE will go low if ISENSE = 195 mV (335 mV). If ISENSE > 275 mV (525 mV), Soft−Start will be initiated.

Gate Drive Output Pin. Capable of driving a 3.0 nF load. GATE is nominally clamped to 13.5 V.

GND Ground Pin.

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