Q67100-Q1185 データシートの表示（PDF） - Siemens AG

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Q67100-Q1185

3.3V 4M x 4-Bit Dynamic RAM 2k & 4k-Refresh

Siemens AG 

3.3V 4M x 4-Bit Dynamic RAM

2k & 4k-Refresh

HYB 3116400BJ/BT(L) -50/-60/-70

HYB 3117400BJ/BT(L) -50/-60/-70

Advanced Information

• 4 194 304 words by 4-bit organization

• 0 to 70 ˚C operating temperature

• Performance:

tRAC RAS access time

tCAC CAS access time

tAA

Access time from address

tRC

Read/Write cycle time

tPC

Fast page mode cycle time

-50 -60 -70

50 60 70 ns

13 15 20 ns

25 30 35 ns

90 110 130 ns

35 40 45 ns

• Single + 3.3 V (± 0.3 V ) supply

• Low power dissipation

max. 396 active mW (HYB 3117400BJ/BT-50)

max. 363 active mW (HYB 3117400BJ/BT-60)

max. 330 active mW (HYB 3117400BJ/BT-70)

max. 360 active mW (HYB 3116400BJ/BT-50)

max. 324 active mW (HYB 3116400BJ/BT-60)

max. 288 active mW (HYB 3116400BJ/BT-70)

7.2 mW standby (LV-TTL)

3.6 mW standby (LV-CMOS)

720 µW standby for L-version

• Output unlatched at cycle end allows two-dimensional chip selection

• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

Self Refresh and test mode

• Fast page mode capability

• All inputs, outputs and clocks fully TTL-compatible

• 2048 refresh cycles / 32 ms for HYB 3117400

4096 refresh cycles / 64 ms for HYB 3116400

• Plastic Package:

P-SOJ-26/24-1 (300 mil)

P-TSOPII-26/24-1 (300 mil)

Semiconductor Group

1

3.96

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