CXD2457R データシートの表示（PDF） - Sony Semiconductor

部品番号

コンポーネント説明

メーカー

CXD2457R

Timing Generator for Progressive Scan CCD Image Sensor

Sony Semiconductor 

CXD2457R

3. Serial data and description of functions

Detailed description

D00

to

D07

CHIP

The serial interface data is loaded to the CXD2457R when D00 and D07 are 1. However, this

assumes that D32 to D39 CHKSUM is satisfied.

D07 D06 D05 D04 D03 D02 D01 D00

Function

1 0 0 0 0 0 0 1 Loading to the CXD2457R

This CTGRY data indicates the functions that the serial interface data controls.

D08

to

D10

CTGRY

D10 D09 D08

Function

0 0 0 Mode control data

0 1 0 Electronic shutter control data

0 1 1 High-speed phase adjustment data (Set all of D11 to D31 to 0.)

1 0 0 System setting data

Input of values other than those listed above is prohibited.

CTGRY: Mode control data

D11

FHIGH

D12

FINE

Detailed description

0: Power saving drive mode

1: High-speed drive mode

When FHIGH = 0, the clock input to CKI is immediately frequency divided by 1/3 and loaded

internally.

Mode switching timing

(5 clocks after the fall of HRI just before XSG is generated)

MCK

CKI

Unstable

Unstable

FHIGH = 1

FHIGH = 0

FHIGH = 1

The high-speed phases of H1, H2, RG, XSHP, XSHD, XRS, ADCLK and other pulses are always

logically the same phase with respect to MCK.

0: DRAFT mode

1: FINE mode

In FINE mode, image data is taken by the normal Progressive Scan method.

In DRAFT mode, image data is taken by pulse elimination readout. This enables a frame rate

three times that during FINE mode. The mode is switched at the fall of HRI just before XSGA.

Note that the FRO output is also switched accordingly. (DRAFT mode: 264H, FINE mode: 792H)

D13

NSG

0: Normal operation

1: Readout prohibited mode

In readout prohibited mode, a readout pulse is not added to V2A and V2B (V2A or V2B takes a

VH value). (V1, V2 and V3 are not modulated.)

The mode is normally switched at the fall of HRI just before the position where the readout pulse

is added.

– 13 –

Share Link: