CXD2457R データシートの表示（PDF） - Sony Semiconductor

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CXD2457R

Timing Generator for Progressive Scan CCD Image Sensor

Sony Semiconductor 

CXD2457R

CTGRY: System setting data

D11

SGXEN

Detailed description

0: Internal SSG (Sync Signal Generator) functions operate to generate FRO and HRO.

1: Internal SSG functions are stopped, and the FRO and HRO pulses are fixed to low.

Note that the STB setting has priority. When the sync signal is input from external CXD2457R,

use it at SGXEN = 1.

D12

EXSG

0: Normal operation

1: XSGA and XSGB are output from the FRO and HRO pins.

Note that the amplitude of the output pulses are VSS to VDDa.

These bits select the pulse output from the ID pin.

D13

to

D14

IDSEL

D14

0

1

0 ID pulse output WEN pulse output

D13

1 XSUB pulse output ID pulse output

XSUB: Inverted SUB pulse output at the amplitude of VSS to VDDa

D15

VTXEN

0: VT (readout clock) is added to V2A, V2B and V3 as normal.

1: VT is not added to V2A, V2B and V3.

During readout, only the modulation necessary for readout is performed.

Note that this setting has priority over mode control data NSG (D13).

0: Checksum is not performed and the checksum data is invalid. (However, dummy data must be

D16

set in the CHKSUM register.)

CHKSUM 1: Checksum is performed. This data is reflected even if the checksum results are NG.

D17

STATUS

0: The EXP pulse is output from the EXP pin.

1: High is indicated if the checksum results are OK, and low if the results are NG.

This pulse is output at the rise of SEN, and reset high at the fall of SEN. This pulse has priority

over mode control data EXP.

D18

to

Input 0.

D20

D21

to

D26

FVFS

These bits set the high-speed sweep period (unit: H) in FS mode.

MSB

LSB

D26 D25 D24 D23 D22 D21

The high-speed sweep is performed 22 times every 1H.

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