MB15F08SL データシートの表示（PDF） - Fujitsu

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MB15F08SL

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F08SL

Table.4 Brinary 11-bit Programmable Counter Data Setting

Divide

ratio

(N)

NNNNNNNNNNN

11 10 9 8 7 6 5 4 3 2 1

3

4

⋅

2047

00000000011

00000000100

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

11111111111

Note: Divide ratio less than 3 is prohibited.

Table.5 Brinary 7-bit Swallow Counter Data Setting

Divide

ratio

(N)

AAAAAAA

7654321

0

0000000

1

0000001

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

127

1111111

Note: Divide ratio (A) range = 0 to 127

Table.6 Prescaler Data Setting

SW = “H”

Prescaler

divide ratio

TX-PLL

RX-PLL

16/17

32/33

SW = “L”

32/33

64/65

Table.7 Phase Comparator Phase Switching Data Setting

FCTX, RX = H

FCTX, RX = L

DoTX, RX

fr > fp

H

L

fr = fp

Z

Z

fr < fp

L

H

VCO Output

Frequency

VCO polarity

(1)

(2)

Note: Z = High-impedance

Depending upon the VCO and LPF polarity, FC bit should be set.

(1)

(2)

LPF Output Voltage

Table.8 LD/fout Output Select Data Setting

LDS

LD/fout output signal

H

fout (frTX, RX, fpTX, RX) signals

L

LD signal

10

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