HD74LV165A データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HD74LV165A

Parallel-Load 8-bit Shift Register

Hitachi -> Renesas Electronics 

HD74LV165A

Parallel-Load 8-bit Shift Register

ADE-205-267 (Z)

1st Edition

March 1999

Description

The HD74LV165A is 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to

each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a

complementary output from the eighth bit.

Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit

function. Holding either of the clock inputs high inhibits clocking, and high enables the other clock input.

Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the

Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register

independent of the state of the clock.

Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook

computers), and the low-power consumption extends the battery life.

Features

• VCC = 2.0 V to 5.5 V operation

• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)

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