LC72140 データシートの表示（PDF） - SANYO -> Panasonic
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LC72140 Datasheet PDF : 15 Pages
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LC72140, 72140M
Table 1. Input data functions
Name
Function
Programmable divider ratio
P15 is the msb. The divider ratio, frequency range and lsb are determined by the setting of the
DVS and SNS flags as shown in Tables 2 and 3. P0 to P3 are ignored if P4 is the Isb.
P0 to P15,
SNS, DVS
Table 2. Divider ratio settings
DVS
SNS
Isb
1
×
P0
0
1
P0
0
0
P4
Note
× =don't care
Divider ratio
272 to 65535
272 to 65535
4 to 4095
Table 3. Frequency range settings
DVS
SNS
Input port
Input frequency range
1
×
FMIN
10 to 160MHz
0
1
AMIN
2 to 40MHz
0
0
AMIN
0.5 to 10MHz
Note
× =don't care
Charge pump control
Bits PDC0 and PDC1 control the charge pump state as shown in Table 4. The sub-change pump
is connected to the gate of the lowpass filter transistor. This can be used in conjunction with PD0
and PD1 (main charge pump) to build a fast locking PLL.
PDC0, PDC1
Table 4. Charge pump state selection
PDC0
PDC1
Charge pump state
0
×
High-impedance
1
1
Operating (operates continuously)
1
0
Operating (when PLL is unlocked)
Note
× =don't care
Reference frequency select
Bits R0 to R3 disable the PLL or select the reference frequency as shown in Table 5.
Table 5. Reference frequency selection
R0 to R3
R3 R2 R1 R0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Reference frequency (kHz)
100
50
25
25
12.5
6.25
3.125
3.125
10
9
5
1
3
30
PLL inhibited and crystal oscillator stopped
PLL inhibited
When the PLL is disabled, the programmable divider is stopped, AMIN and FMIN are pulled to
ground, and the charge-pump outputs become high impedance.
Related bits
UL0, UL1, DLC
Continued on next page.
No.4464–7/15
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