CS61575(2009) データシートの表示（PDF） - Cirrus Logic

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CS61575
(Rev.:2009)

T1/E1 Line Interface

Cirrus Logic 

-XO ¶

&21),'(17,$/

CS61574A CS61575

T PW

T PWH

4#,+

T SU

T H

40/34.%'

Figure 3a. Transmit Clock and Data Switching

Characteristics

T PW

T PWH

!#,+)

Figure 3b. Alternate External Clock Characteristics

T CWH

#3

3#,+

T CC T CH

T CL

T DC

T CDH

3$)

,3"

,3"

T CCH

T CDH

-3"

#/.42/,"94%

$!4!"94%

Figure 4. Serial Port Write Timing Diagram

#3

3#,+

3$/

#,+%

T CDV

Figure 5. Serial Port Read Timing Diagram

T CDZ

()'(:

0#3

,%.4!/3

2,//0,,//0

2#/$%4#/$%

T SU

TH

T PCSL

6!,)$).054$!4!

Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram

8

DS154F3

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