CS61574A データシートの表示（PDF） - Cirrus Logic
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CS61574A Datasheet PDF : 44 Pages
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CS61574A CS61575
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol Min
Typ
Max
Crystal Frequency
(Note 26)
fc
- 6.176000 -
TCLK Frequency
ftclk
-
1.544
-
TCLK Pulse Width
(Note 29) tpwh2
150
-
500
ACLKI Duty Cycle
tpwh3/tpw3
40
-
60
ACLKI Frequency
(Note 30) faclki
-
1.544
-
RCLK Duty Cycle
(Note 31) tpwh1/tpw1
45
50
55
Rise Time, All Digital Outputs
(Note 32)
tr
-
-
85
Fall Time, All Digital Outputs
(Note 32)
tf
-
-
85
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
RPOS/RNEG Valid Before RCLK Falling
(Note 33) tsu1
150
274
-
RDATA Valid Before RCLK Falling
(Note 34) tsu1
150
274
-
RPOS/RNEG Valid Before RCLK Rising
(Note 35) tsu1
150
274
-
RPOS/RNEG Valid After RCLK Falling
(Note 33)
th1
150
274
-
RDATA Valid After RCLK Falling
(Note 34)
th1
150
274
-
RPOS/RNEG Valid After RCLK Rising
(Note 35)
th1
150
274
-
Notes: 29. The transmitted pulse width does not depend on the TCLK duty cycle.
30. ACLKI provided by an external source or TCLK.
31. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
32. At max load of 1.6 mA and 50 pF.
33. Host Mode (CLKE = 1).
34. Extended Hardware Mode.
35. Hardware Mode, or Host Mode (CLKE = 0).
Units
MHz
MHz
ns
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Crystal Frequency
(Note 26)
TCLK Frequency
TCLK Pulse Width
(Note 29)
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
(Note 30)
(Note 31)
Rise Time, All Digital Outputs
(Note 32)
Fall Time, All Digital Outputs
(Note 32)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
(Note 33)
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
(Note 34)
(Note 35)
RPOS/RNEG Valid After RCLK Falling
(Note 33)
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
(Note 34)
(Note 35)
Symbol
fc
ftclk
tpwh2
tpwh3/tpw3
faclki
tpwh1/tpw1
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
Min
Typ
Max Units
-
8.192000 -
MHz
-
2.048
-
MHz
150
-
340 ns
40
-
60
%
-
2.048
-
MHz
45
50
55
%
-
-
85
ns
-
-
85
ns
25
-
-
ns
25
-
100
194
-
ns
-
ns
100
194
100
194
-
ns
-
ns
100
194
-
ns
100
194
100
194
-
ns
-
ns
6
DS154F2
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