CXL1503M データシートの表示（PDF） - Sony Semiconductor
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CXL1503M Datasheet PDF : 9 Pages
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CXL1503M/1505M
Block Diagram
Pin Configuration (Top View)
ABCN 21
ABBL 3
DCAB 23
IN A 22
IN B 24
IN C 2
IN D 6
A. B
CENTER
A. B
BLACK
P. D
5V
CLP
CLP
CLP
CLP
WAVE
FORM
7
5
19
18
48
1 16
TIMING GENERATOR
20 17
P. D
DL A
DL B
DL C
DL D
INPUT
SOURCE
12
PG GEN.
PG GEN.
PG GEN.
PG GEN.
CDS-OUTPUT
CIRCUIT
CDS-OUTPUT
CIRCUIT
15 OUT A
13 OUT B
CDS-OUTPUT
CIRCUIT
11 OUT C
CDS-OUTPUT
CIRCUIT
9 OUT D
POTENTIAL
CONTROL
BIAS.
10 14
VSS 1
IN C 2
ABBL 3
VDD 4
IS 5
IN D 6
CLP 7
VDD 8
OUT D 9
VGG 10
OUT C 11
N.C. 12
24 IN B
23 DCAB
22 IN A
21 ABCN
20 VDD
19 XDL1
18 XDL2
17 VSS
16 VSS
15 OUT A
14 CDS
13 OUT B
Pin Description
No.
Symbol
1, 16, 17 VSS
2
IN C
3
ABBL
4, 8, 20 VDD
5
IS
6
IN D
7
CLP
9
OUT D
10
VGG
11 OUT C
12 N.C.
13 OUT B
14 CDS
15 OUT A
18 XDL2
19 XDL1
21 ABCN
22 IN A
23 DCAB
24 IN B
I/O
Description
— GND
I Signal input C channel
O Autobias DC output for Y signal
— 5V power supply
O Input source DC output
I Signal input D channel
I Clamp pulse input
O Signal output D channel
O Gate bias DC output
O Signal output C channel
—
—
O Signal output B channel
O DC output for CDS
O Signal output A channel
I Clock pulse input 2
I Clock pulse input 1
O Autobias DC output for C signal
I Signal input A channel
I DC bias input for A and B channel
I Signal input B channel
–2–
Impedance (Ω)
> 100k (at no clamp)
2k to 20k
5k
> 100k (at no clamp)
> 100k
50 to 500
2k to 10k
50 to 500
50 to 500
500 to 5k
50 to 500
> 100k
> 100k
2k to 20k
> 100k (at no clamp)
> 100k
> 100k (at no clamp)
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