ML9473 データシートの表示（PDF） - LAPIS Semiconductor Co., Ltd.

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ML9473

1/3, 1/4, 1/5 Duty 60 Output LCD Driver

LAPIS Semiconductor Co., Ltd. 

LAPIS Semiconductor

POWER-ON/OFF TIMING

FEDL9473-01

ML9473

* VLC1, VLC2 are applied when VDD is applied to external bias resistor.

INITIAL SIGNAL TIMING

VDD

BLANK

* Once VDD is applied, BLANK should be applied to ‘L’ level to make all SEGMENTs off until first group of

display data is latched.

8/20

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