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PI74ALVCH16524 データシートの表示(PDF) - Pericom Semiconductor

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PI74ALVCH16524
Pericom-Semiconductor
Pericom Semiconductor Pericom-Semiconductor
PI74ALVCH16524 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
PI74ALVCH16524 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
18-Bit Registered Bus Transceiver
With 3-State Outputs
Product Features
PI74ALVCH16524 is designed for low voltage operation
VCC = 2.3V to 3.6V
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16524 data flow in each direction is controlled
by output-enable (OEAB and OEBA) and clock-enable
(CLKENBA) inputs. For the A-to-B data flow, the data flows
through a single buffer. The B-to-A data can flow through a four-
stage pipeline register path, or through a single register path,
depending on the state of the select (SEL) input.
Data is stored in the internal registers on the low-to-high
transition of the clock (CLK) input, provided that the appropriate
CLKENBA input is low. The B-to-A data transfer is synchronized
with CLK.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH16524 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
CLK 30
CLKENBA 28
OEAB 2
OEBA 27
SEL 55
1 of 18 Channels
A1 3
CE
G1
C1
1
1D
1
CE
C1
1D
CE
C1
1D
CE
C1
1D
54 B1
To 17 Other Channels
1
PS8447A 11/06/00

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