HD74HC75FPEL データシートの表示（PDF） - Renesas Electronics

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HD74HC75FPEL

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Renesas Electronics 

HD74HC75

Quad. Bistable Latches

REJ03D0550-0200

(Previous ADE-205-422)

Rev.2.00

Oct 06, 2005

Description

This latch is ideally suited for use as temporary storage for binary information processing, input/output, and indicator

units. Information present at the data (D) input is transferred to the Q output when the latch enable (LE) is high. The Q

output will follow the data input as long as the enable remains high. When the enable goes low, the information that

was present at the data input at the time the transition occurred is retained at the Q output unit the enable is permitted to

go high again.

Features

• High Speed Operation: tpd (D to Q) = 12.5 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

HD74HC75P

DILP-16 pin

PRDP0016AE-B

(DP-16FV)

P

HD74HC75FPEL SOP-16 pin (JEITA)

PRSP0016DH-B

(FP-16DAV)

FP

HD74HC75RPEL

SOP-16 pin (JEDEC)

PRSP0016DG-A RP

(FP-16DNV)

Note: Please consult the sales office for the above package availability.

Taping Abbreviation

(Quantity)

—

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Function Table

Inputs

Outputs

Data

Latch Enable

Q

Q

L

H

L

H

H

H

H

L

X

L

Q0

Q0

H : High level

L : Low level

X : Irrelevant

Q0, Q0 : Output level before the indicated steady state input conditions were established.

Rev.2.00, Oct 06, 2005 page 1 of 7

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