HD74CDCV857A データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HD74CDCV857A

2.5-V Phase-lock Loop Clock Driver

Hitachi -> Renesas Electronics 

HD74CDCV857A

Recommended Operating Conditions

Item

Symbol Min

Typ

Max

Unit Conditions Notes

Output supply voltage

Supply voltage

DC input signal voltage

High level input voltage

VDDQ

AV

CC

V

IN

V

IHG

2.3

V –0.12

DDQ

–0.3

1.7

2.5

V

DDQ

—

—

2.7

2.7

V +0.3

DDQ

V +0.3

DDQ

V

V

V All pins

1

V PWRDWN

input pin

Low level input voltage

VILG

–0.3

—

0.7

V PWRDWN

input pin

Input differential voltage VID

0.36

—

VDDQ+0.6

V

3

Output differential voltage VOD

0.70

—

VDDQ+0.6

V

Input differential-pair

VIX

VDDQ/2 –0.2 —

VDDQ/2 +0.2 V

2, 3

cross voltage

Output differential-pair

VOX

VDDQ/2 –0.15 —

VDDQ/2 +0.15 V

2, 3

cross voltage

Output current

I

—

—

–12

mA

OH

IOL

—

—

12

mA

Input clock slew rate

tSL(I)

1

—

4

V/ns 20% – 80% 3

Operating temperature

Ta

0

—

70

°C

3

Notes: Inputs pins must be prevent from floating.

Feedback inputs (FBIN, FBIN) may float when the device is in low power mode.

1. DC input signal voltage specifies the allowable dc execution of differential input.

2. Differential cross point voltage is expected to track variations of VDDQ and is the voltage at which

the differential signals must be crossing. (See figure1)

3. Guaranteed by design, not 100% tested in production.

CLK

VID

CLK

Crossing point

Figure 1 Differential input levels

Rev.1 Jun. 2002 page 6 of 13

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