HD74AC194FPEL データシートの表示（PDF） - Renesas Electronics
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HD74AC194FPEL Datasheet PDF : 8 Pages
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HD74AC194
Pin Names
S0, S1
P0 to P3
DSR
DSL
CP
MR
Q0 to Q3
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
Logic Diagram
DSL
P3
P2
S0
P1
P0
DSR
S1
CP
MR
D
C
CQ
CL CL
D
C
CQ
CL CL
D
C
CQ
CL CL
D
C
CQ
CL CL
Q3
Q2
Q1
Q0
Mode Select Table
Inputs
Output
Operating Mode
Reset
MR
S1
L
X
S0
X
DSR
X
DSL
X
Pn
X
Q0
L
Q1
L
Q2
L
Q3
L
Hold
H
L
L
X
X
X
q0
q1
q2
q3
Shift Left
H
H
L
X
L
X
q1
q2
q3
L
H
H
L
X
H
X
q1
q2
q3
H
Shift Right
H
L
H
L
X
X
L
q0
q1
q2
H
L
H
H
X
X
H
q0
q1
q2
Parallel Load
H
H
H
X
X
pn
p0
p1
p2
p3
H : HIGH Voltage Level
L
: LOW Voltage Level
pn (qn) : Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH
clock transition
X : Immaterial
Rev.2.00, Jul.16.2004, page 3 of 7
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