HI3286 データシートの表示（PDF） - Intersil

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HI3286

8-Bit, 160MSPS, Flash A/D Converter

Intersil 

Pin Descriptions (Continued)

PIN

NO SYMBOL I/O

TYPICAL

VOLTAGE LEVEL

16 SELECT2 I DVCC1, DGND1 or Open

17 VOCLP I Clamp Voltage

18

PS

I TTL

13

CLK/E

I PECL/ECL

14 CLK/NE I

48 RESETN/E I

47 RESET/E I

15

CLK/T

I TTL

46 RESETN/T I

44

INV

I TTL

HI3286

EQUIVALENT CIRCUIT

DGND3

13 48

14 47

DVEE3

DVCC1

15 46

OR

44 , 45

DGND1

DVEE3

DVCC1

DESCRIPTION

Data output switching. Data is output

from both PA and PD when left open.

If pin is connected to DVCC1, only PA

is used as output with PB high

impedance. If pin is connected to

DGND1, only PB is used as output with

PA high impedance.

Defines TTL output high level. If left

open the high level is ~ 2.8V.

Power Savings pin. When left open or

at high level the device operates

normally. When set to low level the

power saving mode enabled.

Clock Input.

CLK/E Complementary Input. When

left open, this pin goes to the threshold

potential. Only CLK/E can be used for

operation, but complementary input is

recommended to attain fast and stable

operation.

Reset Input. When the input is set to

low level, the built-in CLK frequency

divider circuit can be reset.

RESETN/E Complementary Input.

When left open, this pin goes to the

threshold voltage. Only RESETN/E

can be used for operation.

Clock input.

Reset Input. When left open, this

input goes to high level. When the

input is set to low level, the built-in

CLK frequency divider circuit can be

reset.

1.5V

Data Output Polarity Inversion Input.

When left open, this input goes to high

level. (See Table 1; I/O

Correspondence Table).

44

DGND1

DVEE3

7

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