HI5741 データシートの表示（PDF） - Renesas Electronics
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HI5741 Datasheet PDF : 13 Pages
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HI5741
0.01F
AVEE
VIN
CIN (OPTIONAL)
CTRL OUT
CTRL IN
REF OUT
RSET
HI5741
FIGURE 22. LOW FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
The signal must have a DC value such that the peak negative
voltage equals -1.25V. Alternately, a capacitor can be placed
in series with REF OUT if a DC multiplying is not required. The
lower input bandwidth can be calculated using the following
formula:
CIN
=
---------------------1----------------------
2 1400 fI N
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 23.
C2
200
AVEE
VIN
C1
50
HI5741
CTRL OUT
CTRL IN
FIGURE 23. HIGH FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
The nominal input/output relationship is defined as:
IOUT
=
-----V----I--N--
80
In order to prevent the full scale output current from exceeding
20.48mA, the RSET resistor must be adjusted according to the
following equation:
RSET
=
----------------------------------1----6---V-----R----E----F-----------------------------------
IOUTFull
scale
–
V-----I--N---8---0P----E----A----K----
The circuit in Figure 23 can be tuned to adjust the lower cutoff
frequency by adjusting capacitor values. Table 1 illustrates the
relationship.
TABLE 1. CAPACITOR SELECTION
fIN
C1
C2
100kHz
0.01F
1F
>1MHz
0.001F
0.1F
Also, the input signal must be limited to 1VP-P to avoid
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
Outputs
The outputs IOUT and IOUT are complementary current outputs.
Current is steered to either IOUT or IOUT in proportion to the
digital input code. The sum of the two currents is always equal to
the full scale current minus one LSB. The current output can be
converted to a voltage by using a load resistor. Both current
outputs should have the same load resistor (64 typically). By
using a 64 load on the output, a 50 effective output resistance
(ROUT) is achieved due to the 227 (15%) parallel resistance
seen looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50 output is needed for matching
the output with a 50 line. The load resistor should be chosen so
that the effective output resistance (ROUT) matches the line
resistance. The output voltage is:
VOUT = IOUT x ROUT.
IOUT is defined in the reference section. IOUT is not trimmed to 14
bits, so it is not recommended that it be used in conjunction with
IOUT in a differential-to-single-ended application. The compliance
range of the output is from -1.25V to 0V, with a 1VP-P voltage
swing allowed within this range.
TABLE 2. INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D13-D0)
IOUT (mA)
IOUT (mA)
11 1111 1111 1111
-20.48
0
10 0000 0000 0000
-10.24
-10.24
00 0000 0000 0000
0
-20.48
Settling Time
The settling time of the HI5741 is measured as the time it takes
for the output of the DAC to settle to within a ±defined error
band of its final value during a 1/16th (code 0000... to 0001
0000.... or 1111... to 1110 1111...) scale transition. In defining
settling time specifications for the HI5741, two levels of accuracy
are considered. The accuracy levels defined for the HI5741 are
12 (or 0.024%) and 13 (0.012%) bits.
Glitch
The output glitch of the HI5741 is measured by summing the
area under the switching transients after an update of the DAC.
Glitch is caused by the time skew between bits of the incoming
digital data. Typically, the switching time of digital inputs are
asymmetrical meaning that the turn off time is faster than the
turn on time (TTL designs). Unequal delay paths through the
device can also cause one current source to change before
another. In order to minimize this, the Intersil HI5741 employs
an internal register, just prior to the current sources, which is
updated on the clock edge. Lastly, the worst case glitch on
traditional D/A converters usually occurs at the major transition
(i.e., code 8191 to 8192). However, due to the split architecture
of the HI5741, the glitch is moved to the 1023 to 1024
FN4071 Rev 12.00
September 20, 2006
Page 10 of 13
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