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HI5804EVAL データシートの表示(PDF) - Intersil

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HI5804EVAL
Intersil
Intersil Intersil
HI5804EVAL Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
HI5804
Electrical Specifications AVCC = DVCC1 = DVCC2 = +5.0V, fS = 5 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, VROUT
Reference Output Current
-
3.5
-
-
-
1
REFERENCE INPUT
Total Reference Resistance, RL
Reference Current
-
7.8
-
-
450
-
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC
Max Output Current (Not to Exceed)
-
2.3
-
-
-
1
DIGITAL INPUT, CLK
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic High Current, IIH
Input Logic Low Current, IIL
Input Capacitance, CIN
DIGITAL OUTPUTS, D0-D11
VCLK = 5V
VCLK = 0V
2.0
-
-
-
-
0.8
-
-
10.0
-
-
10.0
-
7
-
Output Logic Sink Current, IOL
Output Logic Source Current, IOH
Output Capacitance, COUT
TIMING CHARACTERISTICS
VO = 0.4V (Note 2)
1.6
-
-
DVCC2 = 3.0V, VO = 0.4V
-
1.6
-
VO = 2.4V (Note 2)
-0.2
-
-
DVCC2 = 3.0V, VO = 2.4V
-
-0.2
-
-
5
-
Aperture Delay, tAP
Aperture Jitter, tAJ
Data Output Delay, tOD
Data Output Hold, tH
Data Latency, tLAT
Clock Pulse Width (Low)
-
-
-
-
For a Valid Sample (Note 2)
-
5MHz Clock
90
5
-
5
-
8
-
8
-
-
3
100
110
Clock Pulse width (High)
5MHz Clock
90
100
110
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
Digital Supply Voltage, DVCC1
Digital Output Supply Voltage, DVCC2
Total Supply Current, ICC
VIN+ - VIN- = 2V
Analog Supply Current, AICC
VIN+ - VIN- = 2V
Digital Supply Current, DICC1
VIN+ - VIN- = 2V
Digital Output Supply Current, DICC2
VIN+ - VIN- = 2V
Power Dissipation
VIN+ - VIN- = 2V
Offset Error Sensitivity, VOS
Gain Error Sensitivity, FSE
AVCC or DVCC = 5V ±5%
AVCC or DVCC = 5V ±5%
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
4.75
5.0
5.25
4.75
5.0
5.25
2.85
-
5.25
-
60
-
-
46
-
-
13
-
-
1
-
-
300
-
-
± 16
-
-
± 16
-
UNITS
V
mA
k
µA
V
mA
V
V
µA
µA
pF
mA
mA
mA
mA
pF
ns
psRMS
ns
ns
Cycle
ns
ns
V
V
V
mA
mA
mA
mA
mW
LSB
LSB
4

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