HI5804EVAL データシートの表示（PDF） - Intersil
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HI5804EVAL Datasheet PDF : 11 Pages
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HI5804
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NAME
CLK
DVCC1
DGND1
DVCC1
DGND1
AVCC
AGND
VIN+
VIN-
VDC
VROUT
VRIN
AGND
AVCC
D11
DESCRIPTION
Sample Clock Input.
Digital Supply (+5.0V).
Digital Ground.
Digital Supply (+5.0V).
Digital Ground.
Analog Supply (+5.0V).
Analog Ground.
Positive Analog Input.
Negative Analog Input.
DC Bias Voltage Output.
Reference Voltage Output.
Reference Voltage Input.
Analog Ground.
Analog Supply (+5.0V).
Data Bit 11 Output (MSB).
clock which is a non-overlapping two phase signal, φ1 and φ2,
derived from the master clock. During the sampling phase,
φ1, the input signal is applied to the sampling capacitors, CS.
At the same time the holding capacitors, CH, are discharged
to analog ground. At the falling edge of φ1 the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, φ2, the two bottom plates of the sam-
pling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
charge then redistributes between CS and CH completing one
sample-and-hold cycle. The output is a fully-differential, sam-
pled-data representation of the analog input. The circuit not
only performs the sample-and-hold function but will also con-
vert a single-ended input to a fully-differential output for the
converter core. During the sampling phase, the VIN pins see
only the on-resistance of a switch and CS. The relatively
small values of these components result in a typical full
power input bandwidth of 100MHz for the converter.
φ1
VIN +
CS
φ1
CH
φ2
-+
+-
VIN -
φ1
CS
φ1
CH
φ1
VOUT +
VOUT -
φ1
16
D10
Data Bit 10 Output.
17
D9
Data Bit 9 Output.
18
D8
Data Bit 8 Output.
19
D7
Data Bit 7 Output.
20
D6
Data Bit 6 Output.
21
DGND2 Digital Output Ground.
22
DVCC2 Digital Output Supply (+3.0V to +5.0V).
23
D5
Data Bit 5 Output.
24
D4
Data Bit 4 Output.
25
D3
Data Bit 3 Output.
26
D2
Data Bit 2 Output.
27
D1
Data Bit 1 Output.
28
D0
Data Bit 0 Output (LSB).
Detailed Description
Theory of Operation
The HI5804 is a 12-bit, fully-differential, sampling pipeline
A/D converter with digital error correction. Figure 9 depicts
the circuit for the front end differential-in-differential-out sam-
ple-and-hold (S/H). The switches are controlled by an internal
FIGURE 9. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, three identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fourth stage being
only a four bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock sig-
nal is offset by 180 degrees from the previous stage clock
signal with the result that alternate stages in the pipeline will
perform the same operation.
The 4-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final twelve bit output for the converter.
Because of the pipeline nature of this converter, the data on
the bus is output at the 3rd cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each suc-
ceeding sample is output at the following clock pulse. The
output data is synchronized to the external clock by a latch.
The digital outputs are in offset binary format (See Table 1).
7
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