HSP50210JC-52 データシートの表示（PDF） - Renesas Electronics

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HSP50210JC-52

Digital Costas Loop

Renesas Electronics 

HI/LO

SYNC

IIN9-0

QIN9-0

SSYNC

SERCLK

ISER

QSER

LEVEL

DETECT

SYNTHESIZER/

MIXER

M

U

I

X

Q

M

U

X

NCO

MATCHED FILTERING

RRC

M

U

X

RRC

M

U

X

AGC

LOOP

FILTER

I AND D

GAIN ERROR

DETECT

CARTESIAN

TO

POLAR

M

U

X

I2+Q2

I AND D

M

U

X

TAN-1(

Q

I

)

SLICER

SOFSYNC

SOF

COFSYNC

COF

SLOCLK

SERIAL

OUTPUT

FORMATTER

C7-0

8

WR

RD

A2-0

MICROPROCESSOR

INTERFACE

FROM

LOCK

DETECTOR

ACQUISITION

CONTROL

SYMBOL TRACKING

2ND ORDER LOOP

FILTER

CARRIER TRACKING

2ND ORDER LOOP

FILTER

SYMBOL PHASE

ERROR DETECT

CARRIER PHASE

ERROR DETECT

DISCRIMINATOR

FREQUENCY

d

ERROR DETECT

dt

CLK

FRZ_ST

FRZ_CT

LOCK

DETECT

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50210

THRESH

SMBLCLK

AOUT9-0

BOUT9-0

OEA

OEB

LKINT

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