AM24LC02 データシートの表示（PDF） - Anachip Corporation

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AM24LC02

2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM

Anachip Corporation 

2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM

ATC

AM24LC02

Write Operations (Continued)

Write Protection

Programming will not take place if the WP pin of the

AM24LC02 is connected to Vcc. The AM24LC02 will

accept slave and byte addresses; but if the memory

accessed is write protected by the WP pin, the

AM24LC02 will not generate an acknowledge after

the first byte of data has been received, and thus the

programming cycle will not be started when the stop

condition is asserted.

Read Operations

Read operations are initiated in the same way as

write operations with the exception that the R/W bit

of the slave address is set to one. There are three

basic types of read operations: current address read,

random read, and sequential read.

Current Address Read

The AM24LC02 contains an address counter that

maintains the address of the last accessed word,

internally incremented by one. Therefore if the

previous access (either a read or write operation )

was to address n, the next current address read

operation would access data from address n + 1.

Upon receipt of the slave address with R/W bit set to

one, the AM24LC02 issues an acknowledge and

transmits the eight bit data word . The master will

not acknowledge the transfer but does generate a

stop condition and the AM24LC02 discontinues

transmission. (Shown in Figure 6)

Random Read

Random read operations allow the master to access

any memory location in a random manner. To

perform this type of read operation, first the word

address must be set. This is done by sending the

word address to the AM24LC02 as part of a write

operation. After the word address is sent, the master

generates a start condition following the

acknowledge. This terminates the write operation,

but not before the internal address pointer is set.

Then the master issues the control byte again but

with R/W bit set to a one. The AM24LC02 will then

issue an acknowledge and transmit the eight bit data

word. The master will not acknowledge the transfer

but does generate a stop condition and the

AM24LC02 discontinues transmission. (Shown in

Figure 7)

Sequential Read

Sequential read is initiated in the same way as a

random read except that after the AM24LC02

transmits the first data byte, the master issues an

acknowledge as opposed to a stop condition in a

random read. This directs the AM24LC02 to transmit

the next sequentially addressed 8 bit word (Shown

in Figure 8). To provide sequential read the

AM24LC02 contains an internal address pointer

which is incremented by one at the completion of

each operation.

Noise Protection

The SCL and SDA inputs have filter circuits which

suppress noise spikes to assure proper device

operation even on a noisy bus and to avert data

alteration.

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

2/12

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