SST29EE010-150-4C-P2 データシートの表示（PDF） - Silicon Storage Technology
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SST29EE010-150-4C-P2 Datasheet PDF : 27 Pages
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
A11
1
A9
2
A8
3
A13
4
A14
5
NC
6
WE#
7
Vcc
8
NC
9
A16
10
A15
11
A12
12
A7
13
A6
14
A5
15
A4
16
Standard Pinout
Top View
Die up
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
32
OE#
31
A10
30
CE#
29
DQ7
28
DQ6
27
DQ5
26
DQ4
25
DQ3
24
Vss
23
DQ2
22
DQ1
21
DQ0
20
A0
19
A1
18
A2
17
A3
1
2
3
304 MSW F01.1
4
5
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
32-Pin PDIP
25
9 Top View 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
Vcc
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A15 NC WE#
A12 A16 Vcc NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
32-Lead PLCC
25
10
Top View
24
11
23
12
22
13
21
14 15 16 17 18 19 20
DQ1 Vss DQ4 DQ6
DQ2 DQ3 DQ5
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
304 MSW F02.1
6
7
8
9
10
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
11
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
12
A16-A7
Row Address Inputs To provide memory addresses. Row addresses define a page for a
write cycle.
A6-A0
Column Address
Inputs
Column Addresses are toggled to load page data.
13
DQ7-DQ0 Data Input/output
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
14
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
15
WE#
Write Enable
To control the write operations
Vcc
Power Supply
To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V)
for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010
16
Vss
Ground
NC
No Connection
Unconnected pins.
304 PGM T2.0
© 1998 Silicon Storage Technology, Inc.
5
304-04 12/97
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