CAT803(2014) データシートの表示（PDF） - ON Semiconductor

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CAT803
(Rev.:2014)

3-Pin Microprocessor Power Supply Supervisors

ON Semiconductor 

CAT803, CAT809, CAT810

Detailed Descriptions

Reset Timing

The reset signal is asserted LOW for the CAT803/CAT809 and HIGH for the CAT810 when the power supply voltage falls below

the threshold trip voltage and remains asserted for at least 140 ms after the power supply voltage has risen above the threshold.

5V

VTH

VCC

0V

TD

5V

TR

Reset Timeout Period

(140 ms

minimum)

CAT803, CAT809

RESET

0V

CAT810

5V

RESET

0V

Figure 6. Reset Timing Diagram

VCC Transient Response

The CAT803/CAT809/CAT810 protect mPs against

brownout failure. Short duration transients of 4 msec or less

and 100 mV amplitude typically do not cause a false RESET.

Figure 7 shows the maximum pulse duration of negative−

going VCC transients that do not cause a reset condition.

As the amplitude of the transient goes further below the

threshold (increasing VTH − VCC), the maximum pulse

duration decreases. In this test, the VCC starts from an initial

voltage of 0.5 V above the threshold and drops below it by

the amplitude of the overdrive voltage (VTH − VCC).

30

TAMB = 25°C

25

20

15

CAT809Z

10

CAT809M

5

0

1

10

100

1000

RESET OVERDRIVE VTH − VCC (mV)

Figure 7. Maximum Transient Duration without

Causing a Reset Pulse vs. Reset Comparator

Overdrive

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