935267010117 データシートの表示（PDF） - Philips Electronics
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935267010117 Datasheet PDF : 17 Pages
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Philips Semiconductors
Frame Transfer CCD Image Sensor
Objective specification
FXA 1012
Architecture of the FXA 1012
The FXA 1012 consists of an open image section and a storage
section with an optical light shield. An output register and amplifier
are located below the storage section for read-out.
The optical centres of all pixels in the image section form a square
grid. The image area has RGB Bayer colour filter pattern.The charge
is generated and integrated in the image section. This section is
controlled by four image clock phases (A1 to A4). After the integration
time the image charge is shifted one line at a time to the storage
section.
The storage section is controlled by four storage clock phases (B1
to B4). In the still mode the image information is transported straight
through the storage section to the horizontal output register. In the
monitoring mode subsampling of the image is performed at the
image-to-storage transition and the subsampled image is stored in
the storage section. The stored image is shifted one line at a time
into the horizontal output register.
In the next active line time the pixels are transported towards the
output amplifier. Four clock phases (C1 to C4) control the pixel
transport in the output register. In the output amplifier the charge
packets are dumped one by one on a floating diffusion area. The
voltage of this area is sensed and buffered by a three-stage FET
source-follower. Figure 2 shows the detailed internal structure.
Image diagonal (active video only)
Aspect ratio
Active image width x height
Pixel width x height
Image clock pins
Capacity of each clock phase
Number of active lines
Number of black reference lines
Number of dummy lines
Total number of lines
Number of active pixels per line
Number of black reference pixels per line
Total number of pixels per line
IMAGE SECTION
10.4 mm
5:4
8.24 x 6.61 mm2
5.1 x 5.1 µm2
A1, A2, A3, A4
5.4 nF per pin
1296
24 (12+12)
4
1324
1616
72 (2+70)
1688
Cell width x height
Storage clock pins
Capacity of each clock phase
Number of cells per line x number of lines
STORAGE SECTION
5.1 x 5.1 µm2
B1, B2, B3, B4
1.5 nF per pin
1688 x 298
Number of dummy cells
Total number of register cells
Output register clock pins
Capacity of each clock phase
Reset Gate (RG) capacity
Output stage
2000 January
OUTPUT REGISTER
8
1696
C1, C2, C3, C4
60 pF per pin
15 pF
3-stage source follower (open source)
3
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