MAX705(1995) データシートの表示（PDF） - Maxim Integrated

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MAX705
(Rev.:1995)

Low-Cost, μP Supervisory Circuits

Maxim Integrated 

Low-Cost, µP Supervisory Circuits

6

WDI

WATCHDOG

TRANSITION

DETECTOR

VCC

MR 1

250µA

2

VCC

WATCHDOG

TIMER

TIMEBASE FOR

RESET AND

WATCHDOG

RESET

GENERATOR

8

WDO

7

RESET

(RESET)

4

PFI

4.65V*

MAX705

MAX706

MAX813L

5

PFO

1.25V

* 4.40V FOR MAX7O6.

( ) ARE FOR MAX813L ONLY.

3 GND

Figure 1. MAX705/MAX706/MAX813L Block Diagram

VCC

MR 1

250µA

2

VCC

4

PFI

4.65V*

RESET

GENERATOR

MAX707

MAX708

1.25V

* 4.40V FOR MAX7O6.

3 GND

Figure 2. MAX707/MAX708 Block Diagram

8

RESET

7

RESET

5

PFO

_______________Detailed Description

Reset Output

A microprocessor’s (µP’s) reset input starts the µP in a

known state. Whenever the µP is in an unknown state, it

should be held in reset. The MAX705-MAX708/MAX813L

assert reset during power-up and prevent code execu-

tion errors during power-down or brownout conditions.

On power-up, once VCC reaches 1V, RESET is a guaran-

teed logic low of 0.4V or less. As VCC rises, RESET stays

low. When VCC rises above the reset threshold, an inter-

nal timer releases RESET after about 200ms. RESET puls-

es low whenever VCC dips below the reset threshold, i.e.

brownout condition. If brownout occurs in the middle of

a previously initiated reset pulse, the pulse continues for

at least another 140ms. On power-down, once VCC falls

below the reset threshold, RESET stays low and is guar-

anteed to be 0.4V or less until VCC drops below 1V.

The MAX707/MAX708/MAX813L active-high RESET output

is simply the complement of the RESET output, and is

guaranteed to be valid with VCC down to 1.1V. Some µPs,

such as Intel’s 80C51, require an active-high reset pulse.

Watchdog Timer

The MAX705/MAX706/MAX813L watchdog circuit moni-

tors the µP’s activity. If the µP does not toggle the watch-

dog input (WDI) within 1.6sec and WDI is not three-stat-

ed, WDO goes low. As long as RESET is asserted or the

WDI input is three-stated, the watchdog timer will stay

cleared and will not count. As soon as reset is released

and WDI is driven high or low, the timer will start counting.

Pulses as short as 50ns can be detected.

Typically, WDO will be connected to the non-maskable

interrupt input (NMI) of a µP. When VCC drops below

the reset threshold, WDO will go low whether or not the

watchdog timer has timed out yet. Normally this would

trigger an NMI interrupt, but RESET goes low simultane-

ously, and thus overrides the NMI interrupt.

If WDI is left unconnected, WDO can be used as a low-

line output. Since floating WDI disables the internal

timer, WDO goes low only when VCC falls below the

reset threshold, thus functioning as a low-line output.

The MAX705/MAX706 have a watchdog timer and a

RESET output. The MAX707/MAX708 have both active-

high and active-low reset outputs. The MAX813L has

both an active-high reset output and a watchdog timer.

Manual Reset

The manual-reset input (MR) allows reset to be trig-

gered by a pushbutton switch. The switch is effectively

debounced by the 140ms minimum reset pulse width.

MR is TTL/CMOS logic compatible, so it can be driven

by an external logic line. MR can be used to force a

watchdog timeout to generate a reset pulse in the

MAX705/MAX706/MAX813L. Simply connect WDO to

MR.

6 _______________________________________________________________________________________

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