CXD3500R データシートの表示（PDF） - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

Description of Operation

Sync signal input

The HSYNC and VSYNC input pins support separate SYNC only. When using a composite SYNC input,

perform sync separation using a separate sync separation IC, etc.

Clock input

(1) CKI1 and 2 pins

CKI1 and 2 are the clock input pins from an external PLL IC. CKI1 is TTL level input, and CKI2 is small

amplitude clock input. Internal operation is performed at 1/2 clock, so the CXD3500R has a built-in

frequency divider which halves the input master clock, and can select this halved clock or a 1/2 clock input

from an external source by the serial interface setting. However, the input clock should be 55MHz or less,

so when using a master clock of more than 55MHz, input the 1/2 clock.

The 1/N frequency divider output for the PLL IC is output from the HDN pin. The HDN polarity at this time

is set by serial data HDNPOL.

(2) CKI3 pin

CKI3 is the clock input pin when using a scan converter that operates with the input sync signals and an

asynchronous clock in the system. Since two types of clock are input in this case, the circuits that basically

operate with the respective clocks of CKI1 and CKI2 are asynchronous. The input clock should be 55MHz

or less. For details, see the explanation of pulse setting for the scan converter in this data sheet (starting

on page 34).

AC driving of LCD panels for no signal

The following measures have been adopted to allow AC driving of LCD panels even when there is no signal.

However, master clock CKI1 or CKI2 must be input even during free running.

Note that the recommended PLL IC CXA3106(A)Q does not output the clock when there is no HSYNC input.

Horizontal direction pulse

The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is

dependent on the PLL free-running frequency.

Vertical direction pulse

The number of lines is counted by an internal counter and the vertical direction pulses (VST, FRP)

are output at a specified cycle. For the CXD3500R, no signal (free running) status is judged if there is

no VSYNC input for longer than the following periods (free running detection timing).

PLSSL2, 1, 0

L L L or L L H

L H L to H L L

H L H to H H H

V cycle for no signal

701H

1001H

1301H

Free running detection

700H

1000H

1300H

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