CXD3500R データシートの表示（PDF） - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

Input Signal Protocol

1. Horizontal sync signal

a) A standard signal (HSYNC) should be input for each mode.

However, since the CXD3500R requires a double-speed signal as input during NTSC/PAL double-speed

display when not using the built-in double-speed controller, the input specifications at that time are

similar to those for normal data type sync signals, and there should not be a 1/2 offset with respect to

the vertical sync signal.

b) The input sync signal polarity is not fixed, and is set by the serial data (HPOL).

2. Vertical sync signal

a) A sync-separated, normal-speed VSYNC should be input as the vertical sync signal.

b) The input sync signal polarity is not fixed, and is set by the serial data (VPOL).

c) The phase relationship between HSYNC and VSYNC is specified as follows for the CXD3500R.

(1) XGA, Macintosh16, SVGA, VGA, PC-98

HSYNC

VSYNC Sync signal

phase reference

(2) Double-speed NTSC

Double-speed HSYNC

VSYNC Sync signal

phase reference

(3) Double-speed PAL

Double-speed HSYNC

VSYNC Sync signal

phase reference

(4) NTSC

VSYNC

ODD FIELD

HSYNC

EVEN FIELD

Sync signal phase reference

H/2

–8–

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