MAX706ATEPA データシートの表示（PDF） - Maxim Integrated

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MAX706ATEPA

+3V Voltage Monitoring, Low-Cost µP Supervisory Circuits

Maxim Integrated 

+3V Voltage Monitoring, Low-Cost µP

Supervisory Circuits

+3.3V

VCC

+1V

RESET

0V

+3.3V

RESET

0V

+3.3V

MR*

0V

+3.3V

WDO* 0V

VRST VRST

tRST

tRST

tMD

tMR

*NOTE: MR EXTERNALLY DRIVEN LOW.

WDO TIMING SHOWN FOR MAX706P/R/S/T.

Figure 3. RESET, RESET, MR, and WDO Timing

tWP

tWD

+3V/+3.3V

WDI

0V

+3V/+3.3V

WDO

0V

tWD

tWD

+3V/+3.3V

RESET

0V

RESET EXTERNALLY

tRST

TRIGGERED BY MR

Figure 4. MAX706AP/AR/AS/AT Watchdog Timing

+12V +3V/+3.3V

1MΩ

1%

130kΩ

1%

RESET

VCC

(RESET)

MAX706_

MAX708R/S/T

MR

PFI

PFO

GND

TO µP

PARAMETER MIN

+12V RESET

10.24

THRESHOLD AT +25°C

( ) ARE FOR MAX706P/AP

TYP

10.87

MAX

11.50

UNIT

V

Figure 5. Monitoring Both +3V/+3.3V and +12V

MAX706R/S/T

MAX708R/S/T

MAX706AR/AS/AT

RESET

R1

WDO can be connected to the nonmaskable interrupt

(NMI) input of a µP. When VCC drops below the reset

threshold, WDO immediately goes low, even if the

watchdog timer has not timed out (Figure 3). Normally,

this would trigger an NMI, but since reset is asserted

simultaneously, the NMI is overridden. The WDO

should not be connected to RESET directly. Instead,

connect WDO to MR to generate a reset pulse when it

times out.

Manual Reset

The manual reset (MR) input allows RESET and RESET

to be activated by a pushbutton switch. The switch is

effectively debounced by the 140ms minimum reset

pulse width. MR can be driven by an external logic line

since it is TTL/CMOS compatible. The minimum MR

Figure 6. RESET Valid to GND Circuit

input pulse width is 500ns when VCC = +3V and 150ns

when VCC = +5V. Leave MR unconnected or connect

to VCC when not used.

Power-Fail Comparator

The power-fail comparator can be used for various pur-

poses because its output and noninverting input are

not internally connected. The inverting input is internally

connected to a 1.25V reference. The power-fail com-

parator has 10mV of hysteresis, which prevents repeat-

ed triggering of the power-fail output (PFO).

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