IS42S16100-6BLI データシートの表示（PDF） - Integrated Silicon Solution
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IS42S16100-6BLI
Integrated Silicon Solution
IS42S16100-6BLI Datasheet PDF : 81 Pages
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IS42S16100
AC CHARACTERISTICS(1,2,3)
-5
Symbol Parameter
Min. Max.
-6 -7
Min. Max.
Min. Max. Units
tck3
Clock Cycle Time
tck2
tac3
Access Time From CLK(4)
tac2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
5 —
8 —
— 5
— 6
6 —
8 —
— 5.5
— 6
7 — ns
8 — ns
— 5.5 ns
— 6
ns
tchi
CLK HIGH Level Width
2 —
2.5 —
2.5 — ns
tcl
CLK LOW Level Width
toh3 Output Data Hold Time
toh2
CAS Latency = 3
CAS Latency = 2
2 —
2 —
2.5 —
2.5 —
2.0 —
2.5 —
2.5 — ns
2.0 — ns
2.5 — ns
tlz
Output LOW Impedance Time
thz3
Output HIGH Impedance Time(5)
CAS Latency = 3
thz2
CAS Latency = 2
tds
Input Data Setup Time
0 —
— 4
— 6
2 —
0 —
— 5.5
— 6
2 —
0 — ns
— 5.5 ns
— 6
ns
2 — ns
tdh
Input Data Hold Time
1 —
1 —
1 — ns
tas
Address Setup Time
2 —
2 —
2 — ns
tah
Address Hold Time
1 —
1 —
1 — ns
tcks
CKE Setup Time
2 —
2 —
2 — ns
tckh
CKE Hold Time
1 —
1 —
1 — ns
tcka
CKE to CLK Recovery Delay Time 1CLK+3 —
1CLK+3 — 1CLK+3 —
ns
tcs
Command Setup Time (CS, RAS, CAS, WE, DQM)
2 —
2 —
2 — ns
tch
Command Hold Time (CS, RAS, CAS, WE, DQM)
1 —
1 —
1 — ns
trc
Command Period (REF to REF / ACT to ACT)
48 —
54 —
63 — ns
tras
Command Period (ACT to PRE)
32 —
36 100,000 42 100,000 ns
trp
Command Period (PRE to ACT)
16 —
18 —
20 — ns
trcd Active Command To Read / Write Command Delay Time
16 —
16 —
16 — ns
trrd
Command Period (ACT [0] to ACT[1])
11 —
12 —
14 — ns
tdpl3 Input Data To Precharge
Command Delay time
tdpl2
CAS Latency = 3
CAS Latency = 2
— 2CLK
— 2CLK
2CLK —
2CLK —
2CLK — ns
2CLK — ns
tdal3 Input Data To Active / Refresh
CAS Latency = 3 2CLK+trp —
2CLK+trp — 2CLK+trp —
ns
Command Delay time (During Auto-Precharge)
tdal2
CAS Latency = 2 2CLK+trp —
2CLK+trp — 2CLK+trp —
ns
tt
Transition Time
1 10
1 10
1 10 ns
tref
Refresh Cycle Time (2048)
— 32
— 32
— 32 ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after Vdd and Vddq reach their stipulated voltages. Also note that the power-on
sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between Vih (min.) and Vil (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time thz (max.) is defined as the time required for the output voltage to transition by ± 200 mV from Voh (min.) or Vol (max.) when the
output is in the high impedance state.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. D
01/28/08
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