CXD1818 データシートの表示（PDF） - Sony Semiconductor

部品番号

コンポーネント説明

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CXD1818

CD-ROM Decoder

Sony Semiconductor 

CXD1818R

Pin

No.

Symbol

I/O

Logic

108 LRCO O

Classification

CD DSP I/F

109 GRST O

CD DSP I/F

110 XROF

111 TST0

112 TST1

113 TST2

114 TST3

115 VSS

116 TST4

117 TST5

118 TST6

119 TST7

120 VSS

121 VSS

122 XWAT

123 A0

124 A1

125 A2

126 A3

127 A4

128 A5

129 A6

130 VSS

131 D0

132 D1

133 D2

134 D3

135 D4

136 D5

137 D6

138 D7

139 VSS

140 VDD

141 INT

142 XCS

143 XWR

144 XRD

I Negative CD DSP I/F

I

Test I/F

I

Test I/F

I

Test I/F

I

Test I/F

—

—

Power

I

Test I/F

I

Test I/F

I

Test I/F

I

Test I/F

—

—

Power

—

—

Power

O Negative sub CPU I/F

I

sub CPU I/F

I

sub CPU I/F

I

sub CPU I/F

I

sub CPU I/F

I

sub CPU I/F

I

sub CPU I/F

I

sub CPU I/F

—

—

Power

I/O

sub CPU I/F

I/O

sub CPU I/F

I/O

sub CPU I/F

I/O

sub CPU I/F

I/O

sub CPU I/F

I/O

sub CPU I/F

I/O

sub CPU I/F

I/O

sub CPU I/F

—

—

Power

—

—

Power

O Selectable sub CPU I/F

I Negative sub CPU I/F

I Negative sub CPU I/F

I Negative sub CPU I/F

Description

LR clock output to DAC

(connected to the LRCKI pin (Pin 26) of the CXD3000)

GRSCOR resynchronization output

(connected to the SCSY pin (Pin 68) of the CXD3000)

DSP RAM overflow input

(connected to the XROF pin (Pin 45) of the CXD3000)

Test pin 0

Test pin 1

Test pin 2

Test pin 3

VSS

Test pin 4

Test pin 5

Test pin 6

Test pin 7

VSS

VSS

Wait signal for sub CPU buffer memory access

CXD1818R built-in register address bus bit 0

CXD1818R built-in register address bus bit 1

CXD1818R built-in register address bus bit 2

CXD1818R built-in register address bus bit 3

CXD1818R built-in register address bus bit 4

CXD1818R built-in register address bus bit 5

CXD1818R built-in register address bus bit 6

VSS

Sub CPU data bus bit 0

Sub CPU data bus bit 1

Sub CPU data bus bit 2

Sub CPU data bus bit 3

Sub CPU data bus bit 4

Sub CPU data bus bit 5

Sub CPU data bus bit 6

Sub CPU data bus bit 7

VSS

VDD

Interrupt to sub CPU

CXD1818R chip select signal

CXD1818R built-in register write signal

CXD1818R built-in register read signal

–8–

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