74HC132-Q100 データシートの表示（PDF） - NXP Semiconductors.
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74HC132-Q100 Datasheet PDF : 19 Pages
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Nexperia
74HC132-Q100; 74HCT132-Q100
Quad 2-input NAND Schmitt trigger
1.5
ICC
(mA)
1.2
0.9
0.6
0.3
aaa-003893
1.8
ICC
(mA)
1.5
1.2
0.9
0.6
0.3
aaa-003895
0
0
1
2
3
4
5
VIN (V)
0
0
1
2
3
4
5
6
VIN (V)
a. VCC = 4.5 V
b. VCC = 5.5 V
Figure 11. Typical 74HCT132-Q100 transfer characteristics
13 Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd = fi × (tr × ΔICC(AV) + tf × ΔICC(AV)) × VCC where:
Padd = additional power dissipation (μW);
fi = input frequency (MHz);
tr = rise time (ns); 10 % to 90 %;
ΔICC(AV) = average additional supply current (μA).
tf = fall time (ns); 90 % to 10 %;
Average ΔICC(AV) differs with positive or negative input transitions, as shown in Figure 12
and Figure 13.
An example of a relaxation circuit using the 74HC132-Q100; 74HCT132-Q100 is shown
in Figure 14.
74HC_HCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 June 2018
© Nexperia B.V. 2018. All rights reserved.
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