DRP3510A データシートの表示（PDF） - Micronas
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コンポーネント説明
メーカー
DRP3510A Datasheet PDF : 48 Pages
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ADVANCE INFORMATION
Contents, continued
Page
Section
20
6.
20
6.1.
20
6.2.
21
6.3.
21
6.4.
21
6.4.1.
22
6.4.2.
22
6.5.
22
6.6.
24
7.
24
7.1.
24
7.2.
25
7.3.
25
7.3.1.
25
7.3.2.
25
7.3.3.
26
7.4.
26
7.4.1.
26
7.4.2.
27
7.4.3.
27
7.4.4.
28
7.4.5.
28
7.4.6.
29
7.4.7.
29
7.4.8.
30
7.4.9.
30
7.4.10.
30
7.4.11.
31
8.
31
8.1.
31
8.2.
32
9.
32
9.1.
33
9.2.
34
9.3.
34
9.4.
34
9.5.
34
9.6.
34
9.7.
34
9.8.
35
9.9.
35
9.10.
35
9.11.
35
9.12.
35
9.13.
36
10.
Title
Interfaces
The ADR Input Interface
The SDO0 Interface
The SDO1 Interface
The PIO Interface
General Purpose PIO Mode
PIO-DMA Mode
The SP/DIF Interface
Copy Protection
The I2C Interface
The I2C-Data Register
The I2C-Control Register
The I2C Protocol
Controller Writes to the DRP Control Register
Controller Writes to the DRP Data Register
Controller Reads from the DRP Data Register
The I2C Commands
Write into a DRP Register
Default Read Command
Read from a DRP Register
Get ADR Data
Write DMX Data
Write Data into the D0-memory of the DRP
Write Data into the D1-memory of the DRP
Read Data from the D0-memory of the DRP
Read Data from the D1-memory of the DRP
Freeze
The Run Command
Internal Registers and Memory Areas
Default Read (Index and Status)
Digital Volume and Channel Mapping (Write)
Handling of the DRP via Internal Registers
The Internal Fixed Point Number Format
Main Configuration Register 96 (Write)
AGC Register 115 (Read)
Viterbi Min-distance Register 210 (Read)
Clock-deviation Register 244 (Read, Write)
Timing Recovery Control Register 168 (Write)
SP/DIF Configuration Register 83 (Write)
SDO0 Configuration Register 67 (Write)
SO0AUXA Register 69 (Write)
SO0AUXB Register 70 (Write)
SDI1 Input Configuration Register 187 (Write)
SDI1 Input Selection Register 79 (Write)
Actual MPEG Header Register 117 (Read)
Downloading of Programs
Micronas
DRP 3510A
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