AS5SS256K18DQ-9/ET データシートの表示（PDF） - Micross Components

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AS5SS256K18DQ-9/ET

256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through

Micross Components 

SSRAM

AS5SS256K18

CLK

ADSP\

ADSC\

ADDRESS

BWE\, GW\,

BWa\-BWb\

CE\

(Note 2)

READ TIMING

tKC

tKL

tADSS

tKH

tADSH

tADSS

tAS

A1

tAH

tADSH

A2

tCES tCEH tWS tWH

t

AAS

tAAH

ADV\

ADV\ suspends burst.

OE\

High-Z tKQLZ

Q

tOEQ tOEHZ

Q(A1)

tKQ

t

OELZ

tKQ

tKQX

Q(A2)

Q(A2+1)

(NOTE 1)

Q(A2+2)

Q(A2+3)

SINGLE READ

BURST READ

Deselect Cycle

(Note 4)

tKQHZ

Q(A2)

Q(A2+1) Q(A2+2)

Burst wraps around to

its initial state.

NOTE: 1. Q(A2) referes to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence.

4. Outputs are disabled tKQHZ after deselect.

AS5SS256K18

Rev. 2.5 10/13

Micross Components reserves the right to change products or specifications without notice.

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