AT91SAM データシートの表示（PDF） - Atmel Corporation

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AT91SAM

AT91SAM ARM-based Embedded MPU

Atmel Corporation 

D[31,16]on PIOC[31:16] controlled by 2 registers, DELAY3 and DELAY4, located in the HSMC3 user interface

– D[16] <=> DELAY3[3:0],

– D[17] <=> DELAY3[7:4],...,

– D[22] <=> DELAY3[27:24],

– PC[23] <=> DELAY3[31:28]

– D[24] <=> DELAY4[3:0],

– D[25] <=> DELAY4[7:4],...,

– D[30] <=> DELAY4[27:24],

– D[31] <=> DELAY4[31:28]

A[25:0], controlled by 4 registers, DELAY5, DELAY6, DELAY7and DELAY8, located in the HSMC3 user interface

– A[0] <=> DELAY5[3:0],

– A[1] <=> DELAY5[7:4],...,

– A[6] <=> DELAY5[27:24],

– A[7] <=> DELAY5[31:28]

– A[8] <=> DELAY6[3:0],

– A[9] <=> DELAY6[7:4],...,

– A[14] <=> DELAY6[27:24],

– A[15] <=> DELAY6[31:28]

– A[16] <=> DELAY7[3:0],

– A[17] <=> DELAY7[7:4],

– A[18] <=> DELAY7[11:8]

A25 on PC[12] and A[24:19] on PC[7:2]

– A19 <=> DELAY7[15:12],

– A20 <=> DELAY7[19:16],...,

– A23 <=> DELAY7[31:28],

– A24 <=> DELAY8[3:0],

– A25 <=> DELAY8[7:4]

• PIOA User interface

The delay can only be inserted on the HSMCI0 and HSMCI1 I/O lines, so on PA[9:2] and PA[30:23]. The delay is

controlled by 2 registers, DELAY1 and DELAY2, located in the PIOA user interface.

– PA[2] <=> DELAY1[3:0],

– PA[3] <=> DELAY1[7:4],...,

– PA[8] <=> DELAY1[27:24],

– PA[9] <=> DELAY1[31:28]

– PA[23] <=> DELAY2[3:0],

– PA[24] <=> DELAY2[7:4],...,

– PA[29] <=> DELAY2[27:24],

– PA[30] <=> DELAY2[31:28]

SAM9G45 [DATASHEET] 19

6438K–ATARM–12-Feb-13

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