74ALVCH16501 データシートの表示（PDF） - NXP Semiconductors.
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74ALVCH16501 Datasheet PDF : 18 Pages
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NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
Table 2. Pin description …continued
Symbol
Pin
CPBA
30
B0 to B17
54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31
CPAB
55
Description
clock input B-to-A
data inputs or outputs
clock input A-to-B
6. Functional description
6.1 Function table
Table 3. Function table[1]
Inputs
OEAB
LEAB
CPAB
An
L
X
X
X
H
H
X
H
H
H
X
L
H
↓
X
h
H
↓
X
l
H
L
↑
h
H
L
↑
l
H
L
H or L
X
H
L
H or L
X
Output
Bn
Z
H
L
H
L
H
L
H
L
[1] A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA.
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the enable or clock transition;
X = don’t care;
Z = high-impedance OFF-state;
↓ = HIGH-to-LOW clock transition;
↑ = LOW-to-HIGH clock transition.
7. Limiting values
Operating mode
disabled
transparent
latch data and display
clock data and display
hold data and display
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
IIK
input clamping current VI < 0 V
VI
input voltage
control inputs
data inputs
IOK
output clamping current VO > VCC or VO < 0 V
VO
output voltage
IO
output current
VO = 0 V to VCC
ICC
supply current
−0.5
−50
[1] −0.5
[1] −0.5
-
[1] −0.5
-
-
+4.6
V
-
mA
+4.6
V
VCC + 0.5 V
±50
mA
VCC + 0.5 V
±50
mA
100
mA
74ALVCH16501_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 2 April 2010
© NXP B.V. 2010. All rights reserved.
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