UDA1309H データシートの表示（PDF） - Philips Electronics

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UDA1309H

Low-power stereo bitstream ADC/DAC

Philips Electronics 

Philips Semiconductors

Low-power stereo bitstream ADC/DAC

Product specification

UDA1309H

FUNCTIONAL DESCRIPTION

Figure 1 illustrates the various components of the

UDA1309H.

The analog-to-digital converter is a bitstream type

converter, both channels are sampled simultaneously.

The digital-to-analog converter is a BCC (Bitstream

Continuous Calibration) type converter. The digital filter for

the ADC is a bit serial IIR filter that produces a fairly linear

phase response up to 15 kHz. A high-pass filter is

incorporated in the down-sampling path to remove DC

offsets. An overload detection circuit is incorporated to

facilitate automatic recording level adjustment.

The digital up-sample filter for the DAC is partly IIR, with

virtual linear phase response up to 15 kHz, and partly FIR.

A switchable digital de-emphasis circuit is also

incorporated. Due to the BCC principle used, the DAC

needs only single pole post-filtering (one external

capacitor) to meet the out-of-band suppression

requirement.

The ADC and DAC channels have separate power-down

modes, to reduce power if one of them is not in use.

An analog loop-through function enables analog-input

analog-output mode without using the ADC and DAC

converters or filters, thereby switching them off to reduce

power consumption.

The digital interfaces accommodates, 16 and 18-bit,

I2S-bus and LSB justified formats. The ADC digital output

can be made 3-state by means of the ADENB signal, this

enables the use of a digital bus.

The UDA1309H interface accommodates slave mode

only, therefore, the system ICs must provide the system

clock, bit clock and word clock signals. For the DAC, the

UDA1309H accepts the data together with these clocks,

for the ADC it delivers the data in response to these clocks.

Within one stereo frame, the first sample always

represents the left channel. When sending data the

unused bit positions are set to zero, when receiving data

these bit positions are don't cares.

To accommodate the various interface formats and

system clock frequencies four control pins are provided,

MODE0 to MODE2 for mode selection and CLKEDGE

which selects the active edge of the BCK signal. Table 1

gives the interface mode selection, Fig.3 illustrates the

ADC/DAC data formats and Fig.5 the operating modes.

The section of the UDA1309H is designed to

accommodate two main modes:

1. The 256fs mode in which analog-to-digital and

digital-to-analog can be used.

2. The 192fs or 384fs mode (digital-to-analog only).

Table 1 Interface mode selection

DEVICE PIN

MODE 2

0

0

0

0

1

1

1

1

MODE 1

0

0

1

1

0

0

1

1

MODE 0

0

1

0

1

0

1

0

1

Note

1. Only digital-to-analog.

TYPE

LSB justified

LSB justified

LSB justified

LSB justified

I2S-bus

I2S-bus

I2S-bus

I2S-bus

ADC/DAC FORMATS

BITS

16

16

16

18

16

16

16

18

BCK

32fs

64fs

48fs

64fs

32fs

64fs

48fs

64fs

SYS; fsys

256fs

256fs

192fs(1)

256fs

256fs

256fs

384fs(1)

256fs

FIGURE

3(a)

3(b)

4(a)

3(c)

3(d)

3(e)

4(b)

3(f)

Table 2 Clock edge mode

CLKEDGE

0

1

ADC

falling

rising

VALID EDGE OF BCK

DAC

rising

falling

1998 Jan 06

7

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