UDA1309H データシートの表示（PDF） - Philips Electronics

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UDA1309H

Low-power stereo bitstream ADC/DAC

Philips Electronics 

Philips Semiconductors

Low-power stereo bitstream ADC/DAC

Product specification

UDA1309H

handbook, full pagewidth

BCK

WS

SDA

LSB

BCK

WS

SDA

MSB

LEFT

MSB

LEFT

LSB

LSB JUSTIFIED 48fs 16-BIT

LSB

(a)

I2S 48fs 16-BIT

MSB

(b)

RIGHT

MSB

RIGHT

LSB

LSB

MSB

MGE768

Fig.4 DAC and ADC data formats (continued from Fig.3).

There are different modes in which the UDA1309H can operate. These modes can be selected as shown in Table 3 and

Fig.5. In mode a, the digital filters clock is switched off. Switching over to one of the ADC active modes (b, c or d) initiates

a reset sequence of the digital filters. This mode should be activated immediately after power-on for at least 2 clock

periods.

Table 3 Operating mode selection

MODE

DESCRIPTION

a

b

c

d

e

f

g and h

not used

record and playback

record only

record and analog loop-through

analog loop-through

playback only

reserved

Note

1. X = don’t care.

DEVICE PIN LOGIC

ANLPTR

ADPON

DAPON

0

0

0

0

1

1

0

1

0

1

1

0

1

0

0

0

0

1

1

X(1)

1

1998 Jan 06

9

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