CXP84632/84640/84648
Pin
PE5/TO/ADJ
1 pin
PD0 to PD7
PG0 to PG7
PH0 to PH7
24 pins
PI0/INT0
to
PI4/INT4
5 pins
Port E
Circuit format
Internal reset signal
When reset
Port E data
00
“1” when reset TO 01
MPX
ADJ16K∗1 10
ADJ2K∗1 11
Port E function selection (upper)
Port E function selection (lower)
“00” when reset
TO output enable
∗2
High level
( ) with approx.
150kΩ
resistor
when reset
∗1 ADJ signals are frequency dividing output for
32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.
∗2 Pull-up transistor approx. 150kΩ
Port D
Pull-up resistance
∗
Port G
Port H
“0” when reset
Port D, G, H data
Port D, G, H direction
“0” when reset
Data bus
RD (Port D, G, H)
Port I
Pull-up resistance
“0” when reset
Port I data
Hi-Z
IP
∗ Pull-up transistors
approx. 100kΩ
∗
Port I direction
“0” when reset
Data bus
RD (Port I)
INT0
INT1
INT2
INT3
INT4
IP
Hi-Z
∗ Pull-up transistors
approx. 100kΩ
–8–